Computer architectural design has traditionally focused on improving the average-case performance, not time predictability. As a result, some architectural features such as caches, branch prediction, and speculative execution are harmful to time predictability, making accurate worst-case execution time analysis very complicated if not impossible. The recent trend in multicore processor design with shared caches and busses further complicates the worst-case execution time analysis. Therefore, it becomes important to design time-predictable processors to reduce the complexity of worst-case timing analysis while keeping high performance for hard real-time and safety-critical systems.

In this talk, I will introduce two of my recent works in exploring time-predictable cache architectures  for multicore processors and the study of a metric for evaluating architectural time predictability. In the  first work, we have comparatively evaluated four cache architectures, including separated L2 caches,  partitioned L2 caches, a prioritized L2 cache, and a prioritized-partitioned L2 cache for a dual-core  processor. We find that the prioritized-partitioned L2 cache can make a better tradeoff between time  predictability and performance for both real-time and non-real-time threads. In the second work, we  introduce the concept of architectural time predictability (ATP), which separates timing uncertainty  concerns caused by hardware from software. We then propose a metric called Architectural Time-  predictability Factor (ATF) to measure architectural time predictability. Our evaluation on a Very Long  Instruction Word (VLIW) processor indicates that ATF is an effective metric to quantitatively evaluate  architectural time predictability of a whole processor as well as its architectural and microarchitectural  components such as caches, branch prediction, speculative execution, parallel pipelines, and Scratch-  Pad Memory (SPM). Thus ATF can be used to quantitatively guide architectural design for enhancing  time predictability or making better trade-offs between performance and time predictability.

Dr. Wei Zhang is an associate professor in Electrical and Computer Engineering of Virginia Commonwealth University. Dr. Wei Zhang received his Ph.D. from the Pennsylvania State University in 2003. From August 2003 to July 2010, Dr. Zhang worked as an assistant professor and then as an associate professor at Southern Illinois University Carbondale. His research interests are in embedded and real-time computing systems, compiler, computer architecture, and low-power systems. Dr. Zhang has received the 2009 SIUC Excellence through Commitment Outstanding Scholar Award for the College of Engineering, and 2007 IBM Real-time Innovation Award. His research has been supported by NSF, IBM, Intel, Motorola and Altera. He is a senior member of the IEEE. He has served as a member of the organizing or program committees for several IEEE/ACM international conferences and workshops.