Seminars & Colloquia
Computer Science, UC Berkeley, California
The Parallel Computing Landscape: A Berkeley View 2.0"
Monday April 14, 2008 04:00 PM
Location: 3211, EB2 NCSU Centennial Campus
(Visitor parking instructions)
This talk is part of the Triangle Computer Science Distinguished Lecturer Series
To take a fresh approach to the longstanding parallel computing problem, our research agenda will be driven by compelling applications developed by domain experts. Historically, past efforts to resolve these challenges have often been driven "bottom-up" from the hardware, with applications an afterthought. We will focus on exciting new applications that need much more computing horsepower to run well rather than on legacy programs that already run well on today's computers. Our applications are in the areas of personal health, image retrieval, music, speech understanding, and browsers.
The development of parallel software is the heart of the research agenda. The task will be divided into two layers: an efficiency layer that aims at low overhead for 10 percent of the best programmers, and a productivity layer for the rest of the programming community--including domain experts--that reuses the parallel software developed at the efficiency layer. Key to this approach is a layer of libraries and programming frameworks centered around the 13 computational bottlenecks ("dwarfs") that we identified in the Berkeley View report. We will also create a Composition and Coordination Language to make it easier to compose these components. Finally, we will rely on autotuning to map the software efficiently to a particular parallel computer. Past attempts have often relied on a single programming abstraction and language for everyone and on parallelizing compilers.
The role of the operating systems and the architecture in this project is to support software and applications in achieving the ultimate goal, rather than the conventional approach of fixing the environment in which parallel software must survive. Examples include primitives like thin hypervisors and libraries for the operating system and hardware support for partitioning and fast barrier synchronization.
We will prototype the hardware of the future using field programmable gate arrays (FPGAs), which we believe are fast enough to be interesting to parallel software researchers yet flexible enough to "tape out" new designs every day while being cheap enough that university researchers can afford to construct systems containing hundreds of processors. This prototyping infrastructure is called RAMP (Research Accelerator for Multiple Processors), which is being developed by a consortium of universities and companies (see ramp.eecs.berkeley.edu).
He co-authored five books, including two on computer architecture with John L. Hennessy: Computer Architecture: A Quantitative Approach (4 editions, latest is ISBN 0-12-370490-1) and Computer Organization and Design: the Hardware/Software Interface (3 editions; latest is ISBN 1-55860-604-1). They have been widely used as textbooks for graduate and undergraduate courses since 1990.
His work has been recognized by about 25 awards for research, teaching, and service, including Fellow of ACM and IEEE and election to the National Academy of Engineering. In 2005 he shared Japan's Computer & Communication award with Hennessy and was named to the Silicon Valley Engineering Hall of Fame. In 2006 he was elected to the American Academy of Arts and Sciences and the National Academy of Sciences and he received the Distinguished Service Award from the Computing Research Association. In 2007 he was named a Fellow of the Computer History Museum and a Fellow of the American Association for the Advancement of Science.
David Patterson's current projects are the RAD Lab: Reliable Adaptive Distributed systems, RAMP: Research Accelerator for Multiple Processors, and The Berkeley View on Parallel Computing Research.
Special Instructions: !!!THIS TALK HAS BEEN CANCELED!!!
Host: Dinesh Manocha, Computer Science, UNC