Seminars & Colloquia
IBM T. J. Watson Research Center
"Compiler Optimizations For Highly Constrained Multithreaded Multicore Processors"
Monday March 19, 2007 09:30 AM
Location: 3211, EB2 NCSU Centennial Campus
(Visitor parking instructions)
Abstract: As processor performance for general applications starts to plateau due to limiting factors like power and temperature, multicore processors designed for domain specific applications have recently emerged as a promising new technique. They can achieve much higher performance due to simplified and specialized architectural designs. Meanwhile, by pushing part of the complexities to the compiler and adding extra hardware constraints, cores can be clocked much faster and made much smaller. With ample cores on die, these processors are often heavily multithreaded. However, to reap the full benefits of their processing power, it is critical for the compiler to generate efficient code under additional hardware constraints.
In this presentation, I will talk about my research on Intel's IXP processor, which is specially designed for network applications. To take advantage of the packet level parallelism, this processor incorporates many multithreaded cores. Hardware imposes extra constraints on operand fetching, which must be properly handled by the compiler. Threads are simultaneously active to avoid context switch overhead such that long latency operations can be overlapped through fast context switches. However, this mechanism greatly increases register pressure. Moreover, OS is considered too expensive to be installed, although some of the OS services are desperately needed. We proposed a number of compiler techniques to address the hardware constraints, increase resource sharing across threads, and manage thread execution intelligently. Through clever compiler optimizations, we were able to achieve up to 50% performance improvement and eliminate most of the unnecessary stalls (another 20-30% speedup). Some of the optimizations were subsequently implemented by Intel in their research compiler.
Short Bio: Dr. Zhuang is currently a postdoctoral researcher at IBM T.J. Watson Research Center. He received his Ph.D. from Georgia Tech's College of Computing. Xiaotong also holds a BE degree in EE and a MS degree in CS from Shanghai Jiaotong University. His main areas of interest are compiler for high performance computing, embedded systems, compiler and architectural support for security systems, secure architecture. He is also interested in parallel and distributed systems and computer architecture. As a result of his endeavor, Xiaotong has published about 30 papers in conferences and journals.
Host: Frank Mueller, Computer Science, NCSU
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